Topology Generator — AI Fabric

Design mode

Mode GPU (= NIC) count Network design Switch family

Pick GPU count, then a Tree or Rail design and a switch family (51.2T Tomahawk 5, or Jericho3-AI + Ramon3 scheduled fabric); the AMD example, representative switch, tier, and node count are matched at subscription 1:1.16. Inputs below are auto-filled and locked.

Switch input data

Switch / chassis model Spine switch

Leaf model parameters (editable, live)

Label ASIC Kind Scheduled (VOQ) Latency µs/hop Capacity Tbps Slots (chassis)

radix / port count @ speed

@800G @400G @200G @100G

Spine model parameters (editable, live)

Label ASIC Kind Scheduled (VOQ) Latency µs/hop Capacity Tbps Slots (chassis)

radix / port count @ speed

@800G @400G @200G @100G

Load config

Topology & links

Topology Downlink / NIC speed Uplink / fabric speed Nodes per rack (ToR) Blocking factor

Scale

Target nodes NICs per node Node name prefix

Drawing info

Title Project Date

Shown in the drawing title block.

AMD reference design AMD MI3XX Reference Design ↗

Topology Viewer 100%

Topology config output

Bill of Materials (BOM)

Segment	Link speed	Logical links	Switch-port groups	Recommended item	Qty	Source / notes

References

Arista 7060X6-64PE (Tomahawk 5, 64×800G, 51.2 Tbps).
Arista 7800R4 (Jericho3-AI scheduled fabric; 36×800G per line card, 4/8/12/16 slots, up to 576×800G).
FS 800G OSFP to 2×400G QSFP112 breakout DAC · FS 800GBASE 2×DR4/DR8 OSFP optical transceiver.

Radix, blocking, bisection, hop count, and cable count are engineering estimates. Rail-optimized host multihoming and dragonfly are approximated for Slurm tree output; use DOT for the exact graph.